HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 359

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
9.4.3
This register specifies various wait cycles for memory accesses. The bit configuration of this
register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or
TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before
accessing the target area. Specify CSnBCR first, then specify CSnWCR.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
(1)
• CS0WCR, CS6BWCR
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 21
20
19 to 13
12
11
Normal Space, Byte-Selection SRAM
CSn Space Wait Control Register (CSnWCR)
Bit Name
⎯
BAS
⎯
SW1
SW0
Initial
Value
All 0
All 0
0
0
0
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
1: Asserts the WEn (BEn) signal during the read/write
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
and asserts the RD/WR signal during the write access
cycle.
access cycle and asserts the RD/WR signal at the write
timing.
Section 9 Bus State Controller (BSC)
Page 299 of 1414