HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 435

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(b)
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR
to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion
of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which
number is specified by the TRP[1:0] bits in CSnWSR. SDRAM cannot be accessed while in the
self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh
mode has been cleared, command issuance is disabled for the number of cycles specified by the
TRC[1:0] bits in CSnWCR.
Self-refresh timing is shown in figure 9.26. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting
standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is
set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition
from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Self-refreshing
A12/A11*
A25 to A0
D31 to D0
DACKn*
RD/WR
DQMxx
CKIO
RAS
CAS
CSn
Notes:
BS
1
2
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.25 Auto-Refresh Timing
Tp
Tpw
Trr
Hi-z
Trc
Trc
Section 9 Bus State Controller (BSC)
Trc
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