HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 654
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 18 Serial Communication Interface with FIFO (SCIF)
Page 594 of 1414
Bit
6
5
Bit Name Initial Value R/W
CHR
PE
0
0
R/W
R/W
Description
Character Length
Selects seven-bit or eight-bit data.
This bit is only valid in asynchronous mode. In
synchronous mode, the data length is always eight
bits, regardless of the CHR setting.
0: Eight-bit data
1: Seven-bit data*
Note:
Parity Enable
Selects whether to add a parity bit to transmit data
and to check the parity of receive data. This setting is
only valid in asynchronous mode. In synchronous
mode, parity bit addition and checking is not
performed, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked
Note:
* When seven-bit data is selected, the MSB
* When PE is set to 1, an even or odd parity
(bit 7) in SCFTDR is not transmitted.
bit is added to transmit data, depending on
the parity mode (O/E) setting. Receive
data parity is checked according to the
even/odd (O/E) mode setting.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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