HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 238

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Memory Management Unit (MMU)
4.3.2
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
2. When IX = 0, VPN bits 16 to 12 alone are used as the index number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 4.8 and 4.9 show the indexing schemes.
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number
31
0
Virtual address
31
TLB Indexing
VPN(31 to 17)
Index
VPN(11 to 10)
17
Address Array
16
Figure 4.8 TLB Indexing (IX = 1)
12
11
ASID(7 to 0)
0
Exclusive-OR
V
Way 0 to 3
PPN(28 to 10) PR(1 to 0) SZ
PTEH register
31
VPN
Data Array
ASID(4 to 0)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
10
C
0
D
7
Sep 21, 2010
SH
ASID
0