HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 687

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
18.4.4
In synchronous serial communication, data on the communication line is output from a falling
edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge of the
serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the MSB.
In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial
clock.
(1)
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.
(2)
An internal clock generated by the on-chip baud rate generator or an external clock input through
the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1
and CKE0 bits in SCSCR.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed, the clock is fixed high. However, when the operation mode is
reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the
clock high every time one character is transferred, write to the transmit FIFO data register
(SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE
and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data
bytes are transmitted, the clock is fixed high.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
When the external clock is selected:
The SCIF operates on the external clock input through the SCK pin.
Serial clock
Serial data
Data Transfer Format
Clock
Serial Operation in Synchronous Mode
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*
Figure 18.12 Data Format in Synchronous Communication
Note: * High in continuous transmission/reception
LSB
Bit 0
Bit 1
One unit of transfer data (character or frame)
Bit 2
Bit 3
Section 18 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit 5
Bit 6
Bit 7
MSB
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