HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 116

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.5.2
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3
Page 56 of 1414
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Register
indirect with
pre-decrement
CPU Instruction Addressing Modes
Addressing Modes and Effective Addresses for CPU Instructions
Instruction
Format
Rn
@Rn
@Rn+
@–Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn - 1/2/4
+
-
Rn - 1/2/4
Rn
Rn
SH7720 Group, SH7721 Group
⎯
Rn
Rn
After instruction execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 → Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with
Rn after calculation)
R01UH0083EJ0400 Rev. 4.00
Calculation Formula
Sep 21, 2010