HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 36

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 9.39
Figure 9.40
Figure 9.41
Figure 9.42
Figure 9.43
Figure 9.44
Figure 9.45
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
Figure 10.11 DMA Transfer Example in Burst Mode
Figure 10.12 Bus State when Multiple Channels are Operating ................................................ 443
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection ........... 444
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection .......... 444
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection..................... 445
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection.................... 445
Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection................ 446
Figure 10.18 Example of BSC Ordinary Memory Access
Page xxxvi of lx
Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1) .............................................................................................. 395
Example of PCMCIA Space Assignment
(CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10).................................. 396
Basic Timing for PCMCIA I/O Card Interface..................................................... 398
Wait Timing for PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1) .............................................................................................. 399
Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3)........................... 399
Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Wait Cycles inserted in Second and Subsequent Accesses = 1) ........................... 400
Bus Arbitration Timing......................................................................................... 403
Block Diagram of DMAC..................................................................................... 408
DMA Transfer Flowchart ..................................................................................... 425
Round-Robin Mode .............................................................................................. 432
Changes in Channel Priority in Round-Robin Mode ............................................ 433
Data Flow of Dual Address Mode ........................................................................ 435
Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory) .............................. 436
Data Flow in Single Address Mode ...................................................................... 437
Example of DMA Transfer Timing in Single Address Mode............................... 438
DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection) ...................................................... 439
(Dual Address, DREQ Low Level Detection) ...................................................... 440
(Dual Address, DREQ Low Level Detection) ...................................................... 440
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) .............................. 447
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010