HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 196

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 DSP Operating Unit
Table 3.26 Correspondence between Operands and Registers
Note: The multiply operations basically generate 32-bit operation results. So when a register
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic operation. So,
the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure
3.16. In the SH’s standard multiply operations, the lower words of both source operands are input
into a MAC unit. The operation result is also different from the SH’s case. The SH’s multiply
operation result is aligned to the LSB of the destination, but the fixed-point multiply operation
result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always
0.
The fixed-point multiply operation is executed in one cycle. Multiply is always unconditional, but
does not affect any condition code bits, DC, N, Z, V, and GT , in DSR.
• Overflow Protection
Page 136 of 1414
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is
executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean
(+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
Se
⎯
Yes
⎯
⎯
Yes
Yes
Yes
⎯
Sf
⎯
Yes
⎯
⎯
Yes
⎯
Yes
Yes
Dg
Yes
Yes
Yes
Yes
⎯
⎯
⎯
⎯
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010