HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 992

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 A/D Converter
27.3
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRC)
• A/D control/status register (ADCSR)
27.3.1
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are always read as 0.
Table 27.2 indicates the pairings of analog input channels and A/D data registers.
Each ADDR is initialized to H'0000 by a reset and the module standby function and in standby
mode.
Table 27.2 Analog Input Channels and A/D Data Registers
Page 932 of 1414
AN0
AN1
AN2
AN3
Analog Input Channel
A/D Data Registers A to D (ADDRA to ADDRD)
Register Descriptions
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010