HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 145

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(1)
In DSP mode, the following control bits are added to the status register (SR). These added bits are
called DSP extension bits. These DSP extension bits are valid only in DSP mode.
Note: When data is written to the SR register, 0 should be written to bits that are specified as 0.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 28 ⎯
27 to 16 RC11 to
15 to 13 ⎯
12
11
10
9 to 4
3
2
1, 0
Extension of Status Register (SR)
Bit Name
RC0
DSP
MDY
MDX
⎯
FR1
FR0
⎯
Initial
Value
⎯
All 0
⎯
0
0
0
⎯
0
0
⎯
R/W
⎯
R/W
⎯
R/W
R/W
R/W
⎯
R/W
R/W
⎯
Description
DSP Bit
Enables or disables the DSP extended functions. If
this bit is set to 1, the DSP extended functions are
enabled. This bit can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
For details, refer to section 2, CPU.
Repeat Counter
Holds the number of repeat times in order to perform
loop control, and can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
For details, refer to section 2, CPU.
Modulo Control Bits
Enable or disable modulo addressing for X/Y memory
access. These bits can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset,
these bits are initialized to 0. These bits are affected in
the exception handling state.
For details, refer to section 2, CPU.
Repeat Flag Bits
Used by repeat control instructions. These bits can be
modified in privileged mode, privileged DSP mode, or
user DSP mode. At reset, these bits are initialized to 0.
These bits are affected in the exception handling state.
For details, refer to section 2, CPU.
Section 3 DSP Operating Unit
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