HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 63

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Item
Memory
management unit
(MMU)
Cache memory
X/Y memory
Interrupt
controller (INTC)
Bus state
controller (BSC)
Features
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4-Gbyte address space, 256 address spaces (8-bit ASID)
Page unit sharing
Supports multiple page sizes: 1 kbyte or 4 kbytes
128-entry, 4-way set associative TLB
Specifies replacement way by software and supports random replacement
algorithm
Address assignment allows direct access to TLB contents
32-kbyte cache mixing instructions and data
512-entry, 4-way set associative, 16-byte block length
Write-back, write-through, least recent used (LRU) replacement algorithm
Single-stage write-back buffer
User-selectable mapping mechanism
⎯ Fixed mapping for mission-critical realtime applications
⎯ Automatic mapping through TLB for easy to use
Three independent read/write ports
⎯ 8-/16-/32-bit access from CPU
⎯ Up to two 16-bit accesses from DSP
⎯ 8-/16-/32-bit access from DMAC
8-kbyte RAM for X and Y memory individual (4 kbytes × 4)
Seven external interrupt pins (NMI, IRQ5 to IRQ0)
⎯ NMI: Fall/rise selectable
⎯ IRQ: Fall/rise/high level/low level selectable
On-chip peripheral interrupt: Sets priority for each module
Physical address space is provided to support areas of up to 64 Mbytes and
32 Mbytes.
Each area allows independent setting of the following functions:
⎯ Bus size (8, 16, or 32 bits). An access wait cycle count with a different
⎯ Number of access wait cycles. Some areas can be inserted wait cycles
⎯ Sets of idle wait cycle (for the same or different area)
⎯ Supports SRAM, page mode ROM, SDRAM, and pseudo SRAM (ready
⎯ Outputs chip select signals to corresponding areas, such as CS0, CS2 to
size to be supported is provided for each area.
independently in read access and write access.
for page mode) by specifying memory to be connected to each area.
CS4, CS5A/CS5B, and CS6A/CS6B
Section 1 Overview
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