HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 935

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
26.3.5
LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC
panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side
of the panel.
Notes: 1.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 28 ⎯
27, 26
25 to 4
3 to 0
2.
LCDC Start Address Register for Upper Display Data Fetch (LDSARU)
Bit Name
⎯
SAU25 to
SAU4
⎯
The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation
function is not used. Write 0 to the lower nine bits. When using the hardware rotation
function, set the LDSARU value so that the upper-left address of the image is aligned
with the 512-byte boundary.
When the hardware rotation function is used (ROT = 1), set the upper-left address of
the image, which can be calculated from the display image size in this register. The
equation below shows how to calculate the LDSARU value when the image size is 240
× 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but
from the memory size of the image to be displayed. Note that LDLAOR must be a
binary exponential at least as large as the horizontal width of the image. Calculate
backwards using the LDSARU value (LDSARU − 256 (LDLAOR value) × (320 − 1)) to
ensure that the upper-left address of the image is aligned with the 512-byte boundary.
LDSARU = (upper-left address of image) + 256 (LDLAOR value) × 319 (line)
Initial Value
All 0
All 1
All 0
All 0
R/W
R
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Upper Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
Reserved
These bits are always read as 0. The write value
should always be 0.
Section 26 LCD Controller (LCDC)
Page 875 of 1414