HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 14

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.5
9.6
Section 10 Direct Memory Access Controller (DMAC)...................................407
10.1
10.2
10.3
10.4
10.5
Page xiv of lx
9.4.6
9.4.7
9.4.8
Operation .......................................................................................................................... 331
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10
9.5.11
Usage Notes ...................................................................................................................... 404
Features............................................................................................................................. 407
Input/Output Pins.............................................................................................................. 409
Register Descriptions........................................................................................................ 410
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
Operation .......................................................................................................................... 424
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
Usage Notes ...................................................................................................................... 448
10.5.1
10.5.2
10.5.3
Refresh Timer Counter (RTCNT)..................................................................... 329
Refresh Time Constant Register (RTCOR) ...................................................... 330
SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3)...................................... 330
Endian/Access Size and Data Alignment.......................................................... 331
Normal Space Interface..................................................................................... 337
Access Wait Control ......................................................................................... 343
CSn Assert Period Expansion ........................................................................... 345
SDRAM Interface ............................................................................................. 346
Burst ROM (Clock Asynchronous) Interface ................................................... 385
Byte-Selection SRAM Interface ....................................................................... 387
PCMCIA Interface............................................................................................ 392
Burst ROM (Clock Synchronous) Interface...................................................... 400
Wait between Access Cycles ............................................................................ 401
Bus Arbitration ................................................................................................. 401
DMA Source Address Registers (SAR_0 to SAR_5) ....................................... 411
DMA Destination Address Registers (DAR_0 to DAR_5) .............................. 412
DMA Transfer Count Registers (DMATCR_0 to DMATCR_5) ..................... 412
DMA Channel Control Registers (CHCR_0 to CHCR_5)................................ 413
DMA Operation Register (DMAOR) ............................................................... 418
DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)............... 420
DMA Transfer Flow ......................................................................................... 424
DMA Transfer Requests ................................................................................... 426
Channel Priority................................................................................................ 431
DMA Transfer Types........................................................................................ 434
Number of Bus Cycle States and DREQ Pin Sampling Timing ....................... 444
Notes on DACK Pin Output ............................................................................. 448
Notes on the Cases When DACK is Divided.................................................... 449
Other Notes....................................................................................................... 453
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010