HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 65

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Item
16-bit timer pulse
unit (TPU)
Compare match
timer (CMT)
Realtime clock
(RTC)
Serial
communication
interface with
FIFO
(SCIF0, SCIF1)
Infrared data
association
module (IrDA)
I
(IIC)
Serial I/O with
FIFO
(SIOF0, SIOF1)
Analog front end
interface (AFEIF)
2
C bus interface
Features
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Four-channel 16-bit timer
PWM mode
Four types of counter input clocks
Phase counting mode (two channels)
Internal six-channel 32-bit counter (16-/32-bit switchable)
Selectable prescaling for Pφ
Internal full-channel compare match function
Built-in clock, calendar functions, and alarm functions
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Includes a 64-byte FIFO for transmission and another for reception
Supports high-speed UART for Bluetooth
Internal prescaler for Pφ
Conforms to the IrDA 1.0 system
Asynchronous serial communication
On-chip 64-stage FIFO buffers for transmission and reception
Includes a 64-byte FIFO for transmission and another for reception
Supports 8-/16-/16-bit stereo sound input/output
Sampling rate clock input selectable from Pφ and external pin
Includes a prescaler for Pφ
STLC7550 can directly be connected
Data access arrangement function
128-word transmit FIFO
128-word receive FIFO
With interrupt request and DMAC request
With interrupt request and DMAC request
Supports multi master transmission/reception
Interrupt requests and DMAC requests
Section 1 Overview
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