HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 503

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(4)
When the priority is set in fixed mode (CH0 > CH1), even though channel 1 is transferring in burst
mode, if there is a transfer request to channel 0 which has a higher priority, the transfer of channel
0 will begin immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue when
the channel 0 transfer with a higher priority has completely finished.
If channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority
completes the transfer of one transfer unit, the channel 1 transfer will begin again without
releasing the bus mastership. Transfer will then switch between the two in the order of channel 0,
channel 1, channel 0, and channel 1. For the bus state, the CPU cycle after cycle steal mode
transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode
high-priority execution).
This example is illustrated in figure 10.12. If there are channels with conflicting burst transfers,
transfer for the channel with the highest priority is performed first.
In DMA transfer for more than one channel, the DMAC does not give the bus mastership to the
bus master until all conflicting burst transfers have finished.
In round-robin mode, the priority changes according to the specifications shown in figure 10.3.
Note that a channel operating in cycle steal mode cannot be handled together with a channel
operating in burst mode.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bus Mode and Channel Priority
Figure 10.12 Bus State when Multiple Channels are Operating
CPU
CPU
DMA
CH1
DMAC CH1
Burst mode
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
DMA
CH1
DMA
CH0
CH0
DMAC CH0 and CH1
Cycle-steal mode
DMA
CH1
CH1
DMA
CH0
CH0
Section 10 Direct Memory Access Controller (DMAC)
DMA
CH1
DMAC CH1
Burst mode
DMA
CH1
CPU
CPU
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