HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 301

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

SH7720 Group, SH7721 Group

Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010

An instruction assigned at a delay slot of the RTE instruction is executed after the contents of

the SSR is restored into the SR. An acceptance of an exception related to instruction access is

determined according to the SR before restore. An acceptance of other exceptions is

determined by processing mode of the SR after restore, and BL bit value. A processing-

completion type exception is accepted before an instruction at the RTE branch destination

address is executed. However, note that the correct operation cannot be guaranteed if a re-

execution type exception occurs.

In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be

If the MD and BL bits of the SR register are changed by the LDC instruction, an exception is

accepted according to the changed SR value from the next instruction.* A processing-

completion type exception is accepted before the next instruction is executed. An interrupt

and DMA address error in re-execution type exceptions are accepted before the next

instruction is executed.

and an instruction fetch exception is accepted according to the modified SR value.

Section 7 Exception Handling

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