HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 397

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
9.5.2
(1)
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Basic Timing
Normal Space Interface
Figure 9.3 Normal Space Basic Access Timing (Access Wait 0)
Note: * The waveform for DACKn is when active low is specified.
Write
Read
WEn(BEn)
RD/WR
RD/WR
DACKn
CKIO
CSn
RD
BS
A
D
D
*
T1
T2
Section 9 Bus State Controller (BSC)
Page 337 of 1414

Related parts for HD6417720BP133BV