HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 618

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 16 Compare Match Timer (CMT)
16.3.3
In this module, the clock for the counter can be selected from among the following:
•
The clock for the counter is selected by bits CKS2 to CKS0 in CMCSR. CMCNT is incremented
at the rising edge of the selected clock.
16.3.4
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA
transfer or for an internal interrupt to the CPU at a compare match.
A DMA transfer request has different specifications according to the CMT channel as described
below.
1. For channels 0 and 1, a single DMA transfer request is output at a compare match.
2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has
To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling
routine for the CMT interrupt.
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⎯ Peripheral clock (Pφ): 1/8, 1/32, or 1/128
reached the value set in the DMAC, and the output of the request then automatically stops.
For channels 0 to 4:
Timing for Counting by CMCNT
DMA Transfer Requests and Internal Interrupt Requests to CPU
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010