HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 761

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
21.3.9
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15
14
13
12
11
10
9
8
Bit Name
TFWM2
TFWM1
TFWM0
TFUA4
TFUA3
TFUA2
TFUA1
TFUA0
FIFO Control Register (SIFCTR)
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
Transmit FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (full) to B'10000 (empty).
A transfer request to the transmit FIFO is issued by
the TDREQ bit in SISTR.
The transmit FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
transmit FIFO are empty.
Section 21 Serial I/O with FIFO (SIOF)
Page 701 of 1414

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