HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 152

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 DSP Operating Unit
• Example 4: Repeat loop consisting of one instruction
In repeat loops consisting of three instructions, two instructions and one instruction, specific
addresses are specified in the RS register. RE – RS is calculated during SETRC instruction
execution, and the number of instructions included in the repeat loop is determined according to
the result. A value of 0, –2,and –4 in the result correspond to three instructions, two instructions,
and one instruction, respectively.
If repeat instruction execution is completed without branching and if RC[11:0] > 0, an instruction
following the repeat detection instruction is regarded as a repeat start instruction and instruction
execution is repeated for the number of times corresponding to the recognized number of
instructions. If RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is
decremented by 1 and then control is passed to the address specified by the RS register. If
RC[11:0] ==1 (or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and
then the control is passed to the next instruction following the repeat end instruction.
Note: If RE – RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat
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RptDtct:
RptStart:
RptEnd:
loop. (In a repeat loop consisting of four or more instructions, RE – RS is always a
positive value. For details, refer to example 1 above.) If RE – RS is positive, or a value
other than 0, –2,and –4, correct operation cannot be guaranteed.
LDRS RptDtct +8; Sets (repeat detection instruction
LDRE RptDtct +4
SETRC #4
instr0
instr1
; Sets the number of repetitions (4) to
; If RE-RS==-4 during SETRC instruction
; An instruction prior to the Repeat
; [Repeat start instruction]==[Repeat end
execution, the repeat loop is regarded
address + 8) to the RS register
the RC[11:0] bits of the SR register
as one-instruction repeat.
start instruction is regarded as a
repeat detection instruction.
instruction]
; Sets (repeat detection instruction
address + 4) to the RE register
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010