HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 537

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
12.3.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
3. When the frequency control register (FRQCR) is written, the processor stops temporarily. The
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
5. The counter stops at the values H'00.
6. Before changing WTCNT after the execution of the frequency change instruction, always
12.3.3
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
WDT starts counting.
resumes operation. The WOVF flag in WTCSR is not set when this happens.
confirm that the value of WTCNT is H'00 by reading WTCNT.
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
the counter from overflowing.
type of reset specified by the RSTS bit. The counter then resumes counting.
Changing Frequency
Using Watchdog Timer Mode
Section 12 Watchdog Timer (WDT)
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