HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 408

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Section 9 Bus State Controller (BSC)

An address multiplexing is specified so that SDRAM can be connected without external

multiplexing circuitry according to the setting of bits BSZ[1:0]in CSnBCR, AxROW[1:0] and

AxCOL[1:0] in SDCR. Tables 9.12 to 9.17 show the relationship between the settings of bits

BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify

those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.

A25 to A18 are not multiplexed and the original values of address are always output at these pins.

When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address.

Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the

A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B'11), the A0 pin of

SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of

the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.

Page 348 of 1414

Address Multiplexing

Figure 9.13 Example of 16-Bit Data-Width SDRAM Connection

(1M x 16 bits x 4 banks)

SH7720 Group, SH7721 Group

R01UH0083EJ0400 Rev. 4.00

64-Mbit SDRAM

Sep 21, 2010