HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 228

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Section 4 Memory Management Unit (MMU)

The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.

Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with

0s creates the address in the corresponding physical address space.

The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache

and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.

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Address translation not possible

Address translation possible

Non-Cacheable

Privileged mode

Non-Cacheable

Figure 4.2 Virtual Address Space (MMUCR.AT = 1)

External Address

Address translation possible

Address error

Note: Only exists when SR.DSP = 1

SH7720 Group, SH7721 Group

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010