HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 551

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
13.5
13.5.1
Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the
program execution state to software standby mode. In software standby mode, not only the CPU
but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also
halts.
The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip
peripheral modules are, however, initialized. Refer to section 37, List of Registers, for the register
states of the on-chip peripheral modules in software standby mode. The procedure for a transition
to software standby mode is as follows.
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Clear the WDT's timer counter (WTCNT) to 0 and set the CKS2 to CKS0 bits in WTCSR to
3. After the STBY bit in STBCR is set to 1, the SLEEP instruction is executed.
4. Software standby mode is entered and the clocks within the chip are halted. The output of the
13.5.2
Software standby mode is canceled by interrupts (NMI, IRQ (edge detection), RTC, TMU, and
PINT) or a reset.
(1)
The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRQ (edge
detection)*
software standby mode will be canceled after the time set in the WDT's timer control/status
register has elapsed. Both STATUS1 and STATUS0 pins go low. Interrupt exception handling
then begins and a code indicating the interrupt source is set in INTEVT and INTEVT2. After the
branch to the interrupt handling routine, clear the STBY bit in STBCR. WDT stops automatically.
If the STBY bit is not cleared, WDT continues operation and a transition is made to software
standby mode*
STBY bit is cleared. Interrupts are accepted in software standby mode even when the BL bit in SR
is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
Immediately after an interrupt is detected, the phase of the clock output of the CKIO pin may be
unstable, until software standby mode is canceled.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
appropriate values to secure the specified oscillation settling time.
STATUS0 pin and STATUS1 pin go high and low, respectively.
Canceling with Interrupt
Software Standby Mode
Transition to Software Standby Mode
Canceling Software Standby Mode
1
, RTC*
2
when WTCNT reaches H'80. Note that a manual reset is not accepted until the
1
, TMU*
1
, or PINT*
1
interrupt, the clock will be supplied to the entire chip and
Section 13 Power-Down Modes
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