HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 280

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 7 Exception Handling
7.1.4
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
7.1.5
TEA is assigned to address H'FFFFFFFC and the virtual address for an exception occurrence is
stored in this register when an exception related to memory accesses occurs. TEA can be modified
using the software.
Page 220 of 1414
Bit
31 to 12 ⎯
11 to 0
Bit
31 to 0
Interrupt Event Register 2 (INTEVT2)
Exception Address Register (TEA)
INTEVT2
Bit Name
Bit Name
TEA
Initial
Value
All 0
Initial
Value
All 0
R/W
R
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Description
The virtual address for an exception occurrence
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

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