HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 235

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 9 ⎯
8
7, 6
5, 4
3
2
1
0
Bit Name
SV
⎯
RC
⎯
TF
IX
AT
Initial
Value
All 0
0
All 0
All 0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Single Virtual Memory Mode
0: Multiple virtual memory mode
1: Single virtual memory mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Random Counter
A 2-bit random counter that is automatically updated by
hardware according to the following rules in the event of
an MMU exception.
When a TLB miss exception occurs, all of TLB entry
way corresponding to the virtual address at which the
exception occurred are checked. If all ways are valid, 1
is added to RC; if there is one or more invalid way, they
are set by priority from way 0, in the order way 0, way 1,
way 2, way 3. In the event of an MMU exception other
than a TLB miss exception, the way which caused the
exception is set in RC.
Reserved
This bit is always read as 0. The write value should
always be 0.
TLB Flush
Write 1 to flush the TLB (clear all valid bits of the TLB to
0). When they are read, 0 is always returned.
Index Mode
0: VPN bits 16 to 12 are used as the TLB index number.
1: The value obtained by EX-ORing ASID bits 4 to 0 in
Address Translation
Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
PTEH and VPN bits 16 to 12 is used as the TLB
index number.
Section 4 Memory Management Unit (MMU)
Page 175 of 1414