HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 281

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
7.2
7.2.1
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. By executing the return from exception
handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns
to the processor state at the point of interruption and the address where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
1.
2.
3.
4.
5.
6.
7.
8.
The above operations from 1 to 8 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVT. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT or INTEVT2. After the exception handling routine has been
completed, program execution can be resumed by executing an RTE instruction. The RTE
instruction causes the following operations to be executed.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
The contents of PC is saved in SPC.
The contents of SR is saved in SSR.
The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
The mode (MD) bit in SR is set to 1 to place the privileged mode.
The register bank (RB) bit in SR is set to 1.
An exception code identifying the exception event is written to bits 11 to 0 of the exception
event register (EXPEVT); an exception code identifying the interrupt request is written to bits
11 to 0 of the interrupt event register (INTEVT) or interrupt event register 2 (INTEVT2).
If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA
instruction is set to TRA. For an exception related to memory accesses, the logic address
where the exception occurred is written to TEA.*
Instruction execution jumps to the designated exception vector address to invoke the handler
routine.
Exception Handling Function
Exception Handling Flow
1
Section 7 Exception Handling
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