HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 477

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Note:
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
1
0
* Writing 0 is possible to clear the flag.
Bit Name
TE
DE
Initial
Value
0
0
R/W
R/(W)* Transfer End Flag
R/W
Shows that DMA transfer ends. The TE bit is set to 1
when data transfer ends when DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
•
•
To clear the TE bit, the TE bit should be written to 0 after
reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
Writing 0 after TE = 1 read
1: DMA transfer ends by the specified count (DMATCR =
DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and DME
bit in DMAOR to 1. In this time, all of the bits TE, NMIF,
and AE in DMAOR must be 0. In an external request or
peripheral module request, DMA transfer starts if DMA
transfer request is generated by the devices or peripheral
modules after setting the bits DE and DME to 1. In this
case, however, all of the bits TE, NMIF, and AE must be
0, which is the same as in the case of auto request
mode. Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Descriptions
interrupted
0)
DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR is cleared to 0.
DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).
Section 10 Direct Memory Access Controller (DMAC)
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