HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 476

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Direct Memory Access Controller (DMAC)
Page 416 of 1414
Bit
7
6
5
4
3
2
Bit Name
DL
DS
TB
TS1
TS0
IE
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ pin input and
the detecting level.
These bits are valid only in CHCR_0 and CHCR_1.
These bits are always reserved and read as 0 in CHCR_2
to CHCR_5. The write value should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, these bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Transfer Size 1, 0
Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word size (2 bytes)
10: Longword size (4 bytes)
11: 16-byte unit (four longword transfers)
Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010