HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 947

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
11
10
9
Bit Name
MINTS
FINTS
VSINTS
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Memory Access Interrupt State
Indicates the memory access interrupt handling
state.
This bit indicates 1 when the LCDC memory access
interrupt is generated (set state). During the
memory access interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a memory access
1: LCDC has generated a memory access end
Flame End Interrupt State
Indicates the flame end interrupt handling state.
This bit indicates 1 at the time when the LCDC
flame end interrupt is generated (set state). During
the flame end interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a flame end interrupt or
1: LCDC has generated a flame end interrupt and
Indicates the LCDC's Vsync start interrupt handling
state. This bit is set to 1 at the time a Vsync start
interrupt is generated. During the Vsync start
interrupt handling routine, this bit should be cleared
by writing 0 to it.
0: LCDC did not generate a Vsync start interrupt or
1: LCDC has generated a Vsync start interrupt and
Vsync Start Interrupt State
interrupt or has been informed that the generated
memory access interrupt has completed
interrupt and not yet been informed that the
generated memory access interrupt has
completed
has been informed that the generated flame end
interrupt has completed
not yet been informed that the generated flame
end interrupt has completed
has been informed that the generated Vsync
start interrupt has completed
has not yet been informed that the generated
Vsync start interrupt has completed
Section 26 LCD Controller (LCDC)
Page 887 of 1414