HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 835

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
4
3
2
1
0
Bit Name
UE
RD
SF
WDH
SO
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Unrecoverable Error
This bit is set when the host controller detects a system
error that is not related to USB. HCD clears this bit after
the host controller is reset.
0: System error is not generated
1: System error is detected
Resume Detected
This bit is set when the host controller detects that a
device of USB issues a resume signal. This bit is not set
when HCD sets USB Resume state.
0: The resume signal is not detected
1: The resume signal is detected
Start of Frame
This bit is set by the host controller when each frame
starts and after the Hcca Frame Number is updated. The
host controller simultaneously generates the SOF token.
0: Each frame has not initiated or Hcca Frame Number is
1: Initiation of each frame and updating of Hcca Frame
Write-back Done Head
This bit is set immediately after the host controller has
written Hc Done Head to Hcca Done Head. Hcca Done
Head is not updated until this bit is cleared. HCD should
clear this bit only after the content of Hcca Done Head has
been stored.
0: When cleared after set to 1
1: When Hc Done Head is written to Hcca Done head
Scheduling Overrun
This bit is set when the USB schedule has overrun after
Hcca Frame Number has updated. SchedulingOverrun
also increments the SOC bit in USBHCS.
0: The USB schedule has not overrun
1: The USB schedule has overrun
not updated
Number
Section 24 USB Host Controller (USBH)
Page 775 of 1414