HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 185

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

SH7720 Group, SH7721 Group

Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type

of operation and table 3.22 shows the correspondence between each operand and registers.

Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the

ALU fixed-point operations are executed between registers. Each source and destination operand

are selected independently from one of the DSP registers. When a register providing guard bits is

specified as an operand, the guard bits are activated for this type of operation. These operations

are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the

MA stage in which memory access is performed.

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010

base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit

parts when a register not providing the guard-bit parts is specified as the source operand.

When a register not providing the guard-bit parts is specified as a destination operand, the

lower 32 bits of the operation result are input into the destination register.

ALU Fixed-Point Arithmetic Operations

Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow

Section 3 DSP Operating Unit

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