HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 200

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 DSP Operating Unit
Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated even though the specified condition is true and the operation is executed. In case of an
unconditional operation, they are always updated in accordance with the operation result. The
definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit
result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
2. Negative Value Mode: CS[2:0] = B'001
3. Zero Value Mode: CS[2:0] = B'010
4. Overflow Mode: CS[2:0] = B'011
5. Signed Greater Than Mode: CS[2:0] = B'100
6. Signed Greater Than or Equal Mode: CS[2:0] = B'101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is
always cleared in this operation. So is the GT bit.
Page 140 of 1414
The DC bit indicates the last shifted out data as the operation result.
Bit 31 of the operation result is loaded into the DC bit.
The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0.
The DC bit is always cleared to 0.
The DC bit is always cleared to 0.
The DC bit is always cleared.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010