HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 11

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.4
4.5
4.6
4.7
Section 5 Cache..................................................................................................197
5.1
5.2
5.3
5.4
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
4.3.3
4.3.4
MMU Functions................................................................................................................ 182
4.4.1
4.4.2
4.4.3
4.4.4
MMU Exceptions.............................................................................................................. 187
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Memory-Mapped TLB...................................................................................................... 193
4.6.1
4.6.2
4.6.3
Usage Note........................................................................................................................ 195
Features............................................................................................................................. 197
5.1.1
Register Descriptions ........................................................................................................ 199
5.2.1
5.2.2
5.2.3
Operation .......................................................................................................................... 205
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache ................................................................................................... 209
5.4.1
5.4.2
5.4.3
TLB Address Comparison ................................................................................ 179
Page Management Information ......................................................................... 181
MMU Hardware Management .......................................................................... 182
MMU Software Management ........................................................................... 183
MMU Instruction (LDTLB).............................................................................. 183
Avoiding Synonym Problems ........................................................................... 185
TLB Miss Exception ......................................................................................... 187
TLB Protection Violation Exception ................................................................ 188
TLB Invalid Exception ..................................................................................... 189
Initial Page Write Exception ............................................................................. 190
MMU Exception in Repeat Loop...................................................................... 191
Address Array ................................................................................................... 193
Data Array......................................................................................................... 193
Usage Examples................................................................................................ 195
Cache Structure................................................................................................. 197
Cache Control Register 1 (CCR1) .................................................................... 200
Cache Control Register 2 (CCR2) .................................................................... 201
Cache Control Register 3 (CCR3) .................................................................... 204
Searching the Cache.......................................................................................... 205
Read Access ...................................................................................................... 207
Prefetch Operation ............................................................................................ 207
Write Access ..................................................................................................... 207
Write-Back Buffer ............................................................................................ 208
Coherency of Cache and External Memory ...................................................... 208
Address Array ................................................................................................... 209
Data Array......................................................................................................... 210
Usage Examples................................................................................................ 212
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