HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1097

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
31.3.5
TBNCR sets the number of blocks to be transferred when multiblock transfer is specified by bits
TY5 and TY6 in CMDTYR. The contents of TBNCR is decremented for every 1-block transfer
completion. When the contents of TBNCR is 0, the command sequence is terminated, and an
interrupt is generated.
31.3.6
CMDR are six 8-bit registers. A command is written to CMDR as shown in table 31.3, and a
command is transmitted by setting the START bit in CMDSTRT to 1.
Table 31.3 CMDR Configuration
• CMDR0
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15 to 0 TBNCR
Register
CMDR0
CMDR1 to CMDR4
CMDR5
Bit
7
6
5 to 0
Bit Name
Bit Name
Start
Host
INDEX
Transfer Block Number Counter (TBNCR)
Command Registers 0 to 5 (CMDR0 to CMDR5)
Initial
Value
0
0
All 0
Initial
Value
All 0
Contents
Start bit, Host bit, and
command index
Command argument
CRC, End bit
R/W
R/W
R/W
R/W
R/W
R/W
Description
Start bit (This bit should be set to 0)
Transmission bit (This bit should be set to 1)
Command indexes
Description
Transfer Block Number Counter
[Clearing condition]
When the specified number of blocks are transferred and
0 is written to TBNCR.
Operation
Command index writing
Sets the Start bit to 0, and the Host bit to 1.
Command argument writing
Setting of CRC is unnecessary (automatic
calculation)
Setting of end bit is unnecessary (end bit is set to 1)
Section 31 MultiMediaCard Interface (MMCIF)
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