HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 730
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 20 I
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
Page 670 of 1414
(Master output)
(Master output)
(Slave output)
(Slave output)
(Master output)
(Master output)
(Slave output)
(Slave output)
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
processing
processing
ICDRS
ICDRR
RDRF
ICDRS
ICDRR
SCL
SDA
SCL
SDA
User
RDRF
User
SCL
SDA
SDA
SCL
2
C Bus Interface (IIC)
Figure 20.11 Slave Receive Mode Operation Timing (1)
Figure 20.12 Slave Receive Mode Operation Timing (2)
[2] Read ICDRR (dummy read)
A
9
A
9
Bit 7
1
Bit 7
Bit 6
Data 1
1
Data 1
2
Bit 6
Bit 5
2
3
Bit 5
Bit 4
3
4
Bit 4
Bit 3
4
5
[3] Set ACKBT
Bit 3
Bit 2
5
6
Bit 2
Bit 1
6
7
[3] Read ICDRR [4] Read ICDRR
Bit 1
Bit 0
7
8
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Bit 0
A
8
[2] Read ICDRR
A
9
9
Data 1
Sep 21, 2010
Bit 7
Data 1
Data 2
1
Data 2
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