HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 998

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 A/D Converter
27.4.2
Multi mode should be selected when performing A/D conversions on one or more channels. When
the ADST bit in the A/D conversion control/status register (ADCSR) is set to 1 by software, A/D
conversion starts on the first channel (AN0). When two or more channels are selected, after
conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
When A/D conversions end on the selected channels, the ADST bit is cleared to 0. The conversion
results are transferred for storage into the A/D data registers corresponding to the channels.
When the mode or analog input channel selection must be changed during A/D conversion, to
prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in
the group. The ADST bit can be set at the same time as the mode or channel selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 27.3 shows a timing diagram for this example.
1. Start the clock supply to the ADC module (clear the MSTP33 bit in STBCR3 to 0) to run the
2. Multi mode is selected (MULTI = 1), analog input channels AN0 to AN2 are selected (CH1 =
3. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
4. Next, conversion of the second channel (AN1) starts automatically.
5. Conversion proceeds in the same way through the third channel (AN2).
6. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
7. Stop the clock supply to the ADC module (set the MSTP33 bit in STBCR3 to 1) to place the
Page 938 of 1414
ADC module.
1, CH0 = 0), and A/D conversion is started (ADST = 1).
ADDRA.
and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this
time.
ADC in the module standby state.
Multi Mode
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010