HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 99

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
2.2
2.2.1
The LSI supports 32-bit virtual addresses and accesses system resources using the 4-Gbytes of
virtual address space. User programs and data are accessed from the virtual address space. The
virtual address space is divided into several areas as shown in table 2.1.
(1)
This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user
mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0 areas are
handled as address translatable areas.
If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified
while the address translation unit is enabled, the P0 or U0 address is translated into a physical
address based on translation information defined by the user.
If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in
user mode, a transition to an address error exception occurs.
(2)
The P1 area is defined as a cacheable but non-address translatable area. Normally, programs
executed at high speed in privileged mode, such as exception processing handlers, which are at the
core of the operating system (OS), are assigned to the P1 area.
(3)
The P2 area is defined as a non-cacheable but non-address translatable area. A reset processing
program to be called from the reset state is described at the start address (H'A0000000) of the P2
area. Normally, programs such as system initialization routines and OS initiation programs are
assigned to the P2 area. To access a part of an on-chip I/O, its corresponding program should be
assigned to the P2 area.
(4)
The P3 area is defined as a cacheable and address translatable area. This area is used if an address
translation is required for a privileged program.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
P0/U0 Area
P1 Area
P2 Area
P3 Area
Memory Map
Virtual Address Space
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Section 2 CPU