HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 777

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR.
Table 21.8 shows the relationship between the number of channels in control data and bit settings.
Table 21.8 Setting Number of Channels in Control Data
Note: To use only one channel in control data, use channel 0.
21.4.5
Control data performs control command output to the CODEC and status input from the CODEC.
The SIOF supports the following two control data interface methods.
• Control by slot position
• Control by secondary FS
Control data is valid only when data length is specified as 16 bits.
(1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot
position of control data. This method can be used in both SIOF master and slave modes. Figure
21.7 shows an example of the control data interface timing by slot position control.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Number of Channels
1
2
SIOFRxD
SIOFSCK
SIOFSYNC
SIOFTxD
Control by Slot Position (Master Mode 1, Slave Mode 1)
Control Data Interface
Specifications: TRMD[1:0]=00 or 10,
Slot No.0
L-channel
data
Figure 21.7 Control Data Interface (Slot Position)
TDLE=1,
RDLE=1,
CD0E=1,
channel 0
Slot No.1
Control
R-channel
Slot No.2
CD0E
1
1
data
REDG=0,
TDLA[3:0]=0000,
RDLA[3:0]=0000,
CD0A[3:0]=0001,
channel 1
Slot No.3
Control
1 frame
FL[3:0]=1110 (Frame length: 128 bits),
TDRE=1,
RDRE=1,
CD1E=1,
Bit
Section 21 Serial I/O with FIFO (SIOF)
CD1E
0
1
TDRA[3:0]=0010,
RDRA[3:0]=0010,
CD1A[3:0]=0011
Page 717 of 1414

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