HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 509

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
10.5.2
(1)
When DACK is divided for output while the DMAC is accessing an external device, sampling of
DREQ may be accepted once more during the access.
(2)
Conditions: In the cases when DACK is divided for output during external access, specifically, the
following cases:
Any one of the following inter-access idle cycle specifications has been made for that space:
Phenomena: For the access patterns above, the DREQ pin signal is detected with the timing shown
in figures 10.19 and 10.21. For other access patterns, DREQ is detected normally as shown in
figures 10.20 and 10.22.
(3)
1. Detection of DREQ edges: During the bus cycle, input a DREQ edge (rising edge) only once at
2. When overrun-0 in DREQ level detection is specified: During the bus cycle, negate the DREQ
3. When overrun-1 in DREQ level detection is specified: During the bus cycle, negate the DREQ
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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• Idle between write cycles (IWW = 001 or more)
• Idle between read cycles in the same space (IWRRS = 001 or more)
• External wait masking (WM = 0)
For the external accesses under the conditions of 2 above, the problems can be avoided in the
following way:
most.
input after detection of the first DACK output negation but before the second DACK output
negation takes place.
input after detection of the first DACK output assertion but before the second DACK output
assertion takes place.
Overview
Conditions and Phenomena
How to Avoid the Problem
16-byte access
32-bit access in an 8-bit space
16-bit access in an 8-bit space
32-bit access in a 16-bit space,
Notes on the Cases When DACK is Divided
Section 10 Direct Memory Access Controller (DMAC)
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