HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 522

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Clock Pulse Generator (CPG)
Notes: * The input clock is 1.
Page 462 of 1414
Mode
7
1. Use the CKIO frequency within 33.34 MHz ≤ CKIO ≤ 66.67 MHz.
2. The input to divider 1 is the output of PLL circuit 1.
3. Use the internal clock frequency within 33.34 MHz ≤ Iφ ≤ 133.34 MHz.
4. Use the peripheral clock frequency within 8.34 MHz ≤ Pφ ≤ 33.34 MHz.
5. × 1, × 2, × 3, or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2,
FRQCR
Value
1000
1001
1003
1101
1103
1111
1113
1202
1204
1222
1224
1303
1313
1333
Maximum frequency: Iφ = 133.34 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz
The internal clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the IFC bit in FRQCR.
Do not set the internal clock frequency lower than the CKIO pin frequency.
The peripheral clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the PFC bit in FRQCR.
Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
× 1/3, or × 1/4can be selected as the division ratio of an internal clock. × 1, × 1/2, × 1/3,
× 1/4, or
× 1/6 can be selected as the division ratio of a peripheral clock. Set the rate in FRQCR.
PLL
Circuit 1
on (×1)
on (×1)
on (×1)
on (×2)
on (×2)
on (×2)
on (×2)
on (×3)
on (×3)
on (×3)
on (×3)
on (×4)
on (×4)
on (×4)
PLL
Circuit 2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Clock
Ratio*
(I:B:P)
1:1:1
1:1:1/2
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
3:1:1
3:1:1/2
1:1:1
1:1:1/2
4:1:1
2:1:1
1:1:1
Frequency Range of
Input Clock and
Crystal Resonator
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz to 44.45 MHz
33.34 MHz to 44.45 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz
33.34 MHz
SH7720 Group, SH7721 Group
Frequency Range of
CKIO Pin
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz to 44.45 MHz
33.34 MHz to 44.45 MHz
33.34 MHz
33.34 MHz to 66.67 MHz
33.34 MHz
33.34 MHz
33.34 MHz
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010