HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1198

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 33 User Break Controller (UBC)
33.4
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
2. UBC cannot monitor access to the L bus and I bus in the same channel.
3. Note on specification of sequential break:
4. When a user break and another exception occur at the same instruction, which has higher
5. Note the following exception for the above note.
6. Note the following when a break occurs in a delay slot.
7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
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period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired break may not occur. In order to know the timing when the UBC register
is changed, read from the last written register. Instructions after then are valid for the newly
written register value.
A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even
if a bus cycle, in which an A-channel match and a B-channel match occur simultaneously, is
set.
priority is determined according to the priority levels defined in table 7.1 in section 7,
Exception Handling. If an exception with higher priority occurs, the user break is not
generated.
⎯ Pre-execution break has the highest priority.
⎯ When a post-execution break or data access break occurs simultaneously with a re-
⎯ When a post-execution break or data access break occurs simultaneously with a
If a post-execution break or data access break is satisfied by an instruction that generates a
CPU address error (or TLB related exception) by data access, the CPU address error (or TLB
related exception) is given priority to the break. Note that the UBC condition match flag is set
in this case.
If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break
does not occur until the branch destination of the RTE instruction.
UBC registers during UBC module standby mode; the values are not guaranteed.
execution-type exception (including pre-execution break) that has higher priority, the re-
execution-type exception is accepted, and the condition match flag is not set (see the
exception in the following note). The break will occur and the condition match flag will be
set only after the exception source of the re-execution-type exception has been cleared by
the exception handling routine and re-execution of the same instruction has ended.
completion-type exception (TRAPA) that has higher priority, though a break does not
occur, the condition match flag is set.
Usage Notes
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010