HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 868

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 USB Function Controller (USBF)
25.3.1
IFR0 is an interrupt flag register for EP0i, EP0o, EP1, EP2, bus reset, and setup command
reception. When each flag is set to 1 and the interrupt is enabled in the corresponding bit of IER0,
an interrupt request is generated as specified by the corresponding bit in ISR0. Clearing is
performed by writing 0 to the bit to be cleared. Writing 1 is not valid and nothing is changed.
EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2,
respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Page 808 of 1414
Bit
7
6
5
BRST
Bit Name
EP1 FULL
EP2 TR
Interrupt Flag Register 0 (IFR0)
Initial Value
0
0
0
R/W Description
R/W Bus Reset
R
R/W EP2 (Bulk-in) Transfer Request
[Setting condition]
When a bus reset signal is detected on the USB bus.
[Clearing conditions]
•
•
EP1 (Bulk-out) FIFO Full
[Setting condition]
The FIFO buffer of EP1 has a dual-buffer
configuration, and this bit is set when at least one of
the FIFO buffer is full.
[Setting conditions]
•
•
Note: EP1 FULL is a status bit, and cannot be
[Setting condition]
When an IN token is received from the host to EP2
and both of FIFO buffers are empty.
[Clearing conditions]
•
•
When reset
When 0 is written to by CPU
When reset
When both FIFO buffers are empty.
When reset
When 0 is written to by CPU
cleared.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010