HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 23

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.4
25.5
25.6
25.7
25.8
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
25.3.16 EP0i Data Register (EPDR0i) ........................................................................... 821
25.3.17 EP0o Data Register (EPDR0o) ......................................................................... 821
25.3.18 EP0s Data Register (EPDR0s) .......................................................................... 821
25.3.19 EP1 Data Register (EPDR1) ............................................................................. 822
25.3.20 EP2 Data Register (EPDR2) ............................................................................. 822
25.3.21 EP3 Data Register (EPDR3) ............................................................................. 822
25.3.22 EP4 Data Register (EPDR4) ............................................................................. 823
25.3.23 EP5 Data Register (EPDR5) ............................................................................. 823
25.3.24 EP0o Receive Data Size Register (EPSZ0o)..................................................... 823
25.3.25 EP1 Receive Data Size Register (EPSZ1) ........................................................ 824
25.3.26 EP4 Receive Data Size Register (EPSZ4) ........................................................ 824
25.3.27 Trigger Register (TRG)..................................................................................... 824
25.3.28 Data Status Register (DASTS).......................................................................... 825
25.3.29 FIFO Clear Register 0 (FCLR0) ....................................................................... 825
25.3.30 FIFO Clear Register 1 (FCLR1) ....................................................................... 826
25.3.31 DMA Transfer Setting Register (DMA) ........................................................... 826
25.3.32 Endpoint Stall Register 0 (EPSTL0) ................................................................. 827
25.3.33 Endpoint Stall Register 1 (EPSTL1) ................................................................. 828
25.3.34 Configuration Value Register (CVR)................................................................ 828
25.3.35 Time Stamp Register (TSRH/TSRL) ................................................................ 829
25.3.36 Control Register 0 (CTLR0) ............................................................................. 830
25.3.37 Control Register 1 (CTLR1) ............................................................................. 831
25.3.38 Endpoint Information Register (EPIR) ............................................................. 831
25.3.39 Timer Register (TMRH/TMRL) ....................................................................... 836
25.3.40 Set Time Out Register (STOH/STOL).............................................................. 836
Operation .......................................................................................................................... 837
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.4.6
EP4 Isochronous-Out Transfer.......................................................................................... 849
EP5 Isochronous-In Transfer ............................................................................................ 852
Processing of USB Standard Commands and Class/Vendor Commands ......................... 855
25.7.1
Stall Operations................................................................................................................. 856
25.8.1
25.8.2
25.8.3
Cable Connection.............................................................................................. 837
Cable Disconnection ......................................................................................... 838
Control Transfer................................................................................................ 839
EP1 Bulk-Out Transfer (Dual FIFOs)............................................................... 845
EP2 Bulk-In Transfer (Dual FIFOs) ................................................................. 846
EP3 Interrupt-In Transfer.................................................................................. 848
Processing of Commands Transmitted by Control Transfer ............................. 855
Overview........................................................................................................... 856
Forcible Stall by Application ............................................................................ 856
Automatic Stall by USB Function Controller ................................................... 858
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