HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 493

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
transfer).
waiting)
(channel 3 waits for transfer).
3 becomes the lowest priority.
Transfer request
(1) Channels 0 and 3
Figure 10.4 Changes in Channel Priority in Round-Robin Mode
(3) Channel 1
Waiting channel(s) DMAC operation
1,3
3
3
None
(2) Channel 0 transfer
(4) Channel 0 transfer
(5) Channel 1 transfer
(6) Channel 1 transfer
(7) Channel 3 transfer
(8) Channel 3 transfer
starts
ends
starts
ends
starts
ends
Section 10 Direct Memory Access Controller (DMAC)
Priority order
changes
Priority order
changes
Priority order
changes
Channel priority
0 > 1 > 2 > 3 > 4 > 5
1 > 2 > 3 > 4 > 5 > 0
2 > 3 > 4 > 5 > 0 > 1
4 > 5 > 0 > 1 > 2 > 3
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