HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 891

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
25.3.37 Control Register 1 (CTLR1)
CTLR1 makes settings of internal timer which is used in the isochronous transfer.
25.3.38 Endpoint Information Register (EPIR)
EPIR is a register to set the configuration information for each endpoint. 5 bytes of the
information are required for one endpoint and the formats are listed in tables 25.3 and 25.4. Write
the data in order from endpoint 0. Do not write more than 5 (bytes) × 10 (endpoints) = 50 bytes.
Write this information once at power-on reset. Do not write it again afterwards.
Write data of one endpoint is described below. EPIR writes data in the same address in order.
Therefore though there is only one EPIR register, write data for registration number N (N is from
0 to 9) is listed as EPIRN0 to EPIRN4 (EPIR [registration number] [write order]) for the purpose
of explaining. Write data in order from EPIR00.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
7 to 2
1
0
Bit
name
⎯
TMR ACLR
TMR EN
Initial
value
All 0
1
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Auto Clear
Selects method to clear TMR (timer register).
0: Not cleared. When clearing TMR, write 0 to TMR by
1: Automatically cleared every time when SOF is
Timer Enable
TMR EN is TMR (timer register) enable bit.
0: Timer operation is disabled
1: Timer operation is enabled
CPU.
received.
Section 25 USB Function Controller (USBF)
Page 831 of 1414