HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 711

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
20.3.1
ICCR1 enables or disables the I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
7
6
5
4
3 to 0
Bit Name
ICE
RCVD
MST
TRS
⎯
I
2
C Bus Control Register 1 (ICCR1)
Initial
Value
0
0
0
0
All 0
2
C bus interface, controls transmission or reception, and selects
R/W
R/W
R/W
R/W
R/W
R
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations.
Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1.
Operating modes are described below according to MST
and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Reserved
These bits are always read as 0. The write value should
always be 0.
2
C Bus Interface Enable
2
C bus format, when arbitration
Section 20 I
2
C Bus Interface (IIC)
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