HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1079

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Section 30 SIM Card Module (SIM)
(6)
Data Transfer Using DMAC
The smart card interface enables reception and transmission using the DMAC.
In transmission, when the TDRE flag in SCSSR is set to 1, a DMA transfer request for transmit
data empty is issued. If a DMA transfer request for transmit data empty is set in advance as a
DMAC activation source, the DMAC can be activated and made to transfer data when a DMA
transfer request for transmit data empty occurs.
When in T = 0 mode and if an error signal is received during transmission, the same data is
automatically retransmitted. At the time of this retransmission, no DMA transfer request is issued,
and so the number of bytes specified to the DMAC can be transmitted.
When using the DMAC for transmit data processing and performing error processing as a result of
an interrupt request sent to the CPU, the TIE bit should be cleared to 0 so that no TXI requests are
generated, and the RIE bit should be set to 1 so that an ERI request is issued. The ERS flag set
when an error signal is received is not cleared automatically, and so should be cleared by sending
an interrupt request to the CPU.
In receive operation, when the RDRF flag in SCSSR is set to 1, a DMA transfer request for
receive data full is issued. By setting a DMA transfer request for receive data full in advance as a
DMAC activation source, the DMAC can be activated and made to transfer data when a DMA
transfer request for receive data full occurs.
When in T = 0 mode and if a parity error occurs during reception, a data retransmit request is
issued. At this time the RDRF flag is not set, and a DMA transfer request is not issued, so the
number of bytes specified to the DMAC can be received.
When using the DMAC for receive data processing and performing error processing as a result of
an interrupt request sent to the CPU, the RIE bit should be set to 1 and the EIO bit to 1, so that no
RXI requests are generated and only ERI requests are generated.
The PER, ORER, and WAIT_ER flags that are set by a receive error are not automatically cleared,
and so should be cleared by sending an interrupt request to the CPU.
When using the DMAC for transmission and reception, the DMAC should always be set first and
put into the enabled state, before setting the smart card interface.
R01UH0083EJ0400 Rev. 4.00
Page 1019 of 1414
Sep 21, 2010