HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1104

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 MultiMediaCard Interface (MMCIF)
31.3.11 Data Timeout Register (DTOUTR)
DTOUTR specifies a cycle to generate a data timeout. The 16-bit counter (DTOUTC) and a
prescaler count the peripheral clock to monitor the data timeout. The prescaler always counts the
peripheral clock, and outputs a count pulse for every 10000 peripheral clocks. The initial value of
DTOUTC is 0, and DTOUTC starts counting the prescaler output from the start of the command
sequence. DTOUTC is cleared when the command sequence has ended, or when the command
sequence has been aborted by setting the CMDOFF bit to 1, after which DTOUTC stops counting
the prescaler output.
When the command sequence does not end, DTOUTC continues counting the prescaler output,
and enters the data timeout error states when the number of prescaler output reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. To perform data timeout error handling, the command sequence should be aborted by
setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent extra-interrupt
generation.
For a command with data busy state, as the command sequence is terminated before entering the
data busy state, data timeout cannot be monitored. Timeout in the data busy state should be
monitored by firmware. When DTOUTR is set to 0, a data timeout is generated immediately after
the command sequence has started.
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Bit
15 to 0 DTOUTR All 1
Bit Name
Initial
Value
R/W Description
R/W Data timeout time/10000
Data timeout time is determined by peripheral clock cycle ×
DTOUTR setting value × 10000.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010