HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 274

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 X/Y Memory
• Priority order
6.2
6.2.1
Methods for accessing by the CPU are directly via the L bus from the virtual addresses, and via
the I bus after the virtual addresses are converted to be the physical addresses using the MMU. As
long as a conflict on the page does not occur, access via the L bus is performed in one cycle.
Several cycles are necessary for accessing via the I bus. According to the CPU operating mode,
access from the CPU is as follows:
(1)
The X/Y memory can be accessed by the CPU directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
(2)
The X/Y memory can be accessed by the CPU directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
(3)
The MMU can be used to map the virtual addresses in space U0 to this memory.
6.2.2
Methods for accessing from the DSP differ according to instructions.
With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always
accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X
bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory
access via the Y bus can be performed simultaneously.
In the case of a single data transfer instruction, methods for accessing from the DSP are directly
via the L bus from the virtual addresses, and via the I bus after the virtual addresses are converted
to be the physical addresses using the MMU. As long as a conflict on the page does not occur,
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In the event of simultaneous accesses to the same page from different buses, the accesses are
processed according to the priority order. The priority order is: I bus > X bus > L bus in the X
memory and I bus > Y bus > L bus in the Y memory.
Privileged mode and privileged DSP mode (SR. MD = 1)
User DSP mode (SR.MD = 0 and SR.DSP = 1)
User mode (SR.MD = 0 and SR.DSP = 0)
Operation
Access from CPU
Access from DSP
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010